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Learn how to program NAND and NOR logic gates step‑by‑step using CODESYS PLC software. In this tutorial, you’ll understand ladder logic design, Boolean logic structure, and practical control examples for automation engineers and beginners.
What You’ll Learn:
Setting up logic in CODESYS
Creating NAND & NOR ladder diagrams
Real‑time simulation and testing
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0:00
[Music]
0:05
Hello everyone, welcome to automation
0:08
community. Today in this video we are
0:12
going to discuss about universal logic
0:14
gates that is nor and n. So let's start
0:21
norate. Ngate is the combination of or
0:25
and not gates. As you can see in the
0:28
table, when both the inputs are false,
0:32
then only the output is true. And when
0:36
only one input is true and another is
0:38
false, then the output is also false.
0:42
And when both the inputs are true, then
0:45
also the output is false. So for the
0:48
output Y to be on
0:51
both the inputs should be off and then
0:54
only output Y will be on. So for
0:57
norlogic gate the output Y will be will
1:01
turn on only if when the two inputs are
1:05
off.
1:06
So if any one of the input is true or
1:09
all the inputs are true then the output
1:12
Y will not be on it will be off. And
1:15
then NAND gate. NAND gate is the
1:19
combination of and and not gates. As you
1:22
can see in the table, when both the
1:24
inputs are false, then the output Y is
1:28
also true.
1:31
And when any one of the input is true,
1:34
that means B is true and A is false or B
1:38
is off and A is on then also the output
1:42
Y will be on. And when both the inputs
1:46
are true then the output Y will not be
1:49
off. So for for an anal logic gate the
1:52
output Y turns on when all the inputs
1:55
are false or any one of the input is
1:59
false then only the output Y will be
2:02
true.
2:04
So let's move to codices where we will
2:06
draw the ladder diagram of NOR and NAND
2:11
gate and also simulate them.
2:14
I will open cortices.
2:27
We will create a new project.
2:32
Okay. So we need to select a standard
2:36
project and then click on okay.
2:42
You have to select landed uh logic
2:44
diagram here and click okay.
2:50
After that go to PLC PRG here. Double
2:53
click on it and then here we will draw
2:55
the ladder diagram.
2:58
So to implement no logic gate we will be
3:01
using normally closed contacts and these
3:04
normally closed contacts will be
3:06
connected in series. So that we will
3:10
implement nor logic gate. So let's see
3:15
we will insert a negated coil and then
3:18
here we will insert one more negated
3:20
coil and then we will insert a coil.
3:24
So this will be input
3:27
one. Okay.
3:30
And then this will be
3:33
input
3:35
two.
3:37
Okay. And this will be output
3:43
one.
3:46
So as you can see here
4:02
this output one will be on when both the
4:05
inputs are false.
4:08
So if any one of the input is true,
4:13
let's say input one is true. So this
4:16
input one we have used it as normally
4:18
closed contact. It is a negated contact.
4:21
So when in true state, it will not allow
4:23
signal to pass through it. As a result,
4:26
output one will not turn on. Similarly,
4:29
if input two is true, then as a normally
4:33
closed contact, it won't allow signal to
4:36
pass through it. As a result, this
4:37
output one will be false.
4:41
And let's say both the inputs are true.
4:44
So these both inputs are used as
4:46
normally closed contacts. Neither of the
4:49
input will allow neither of the normally
4:51
closed contact will allow signal to pass
4:53
through it. As a result, output one will
4:56
not turn on. So for output one to be on,
4:59
both the inputs should be false. So in
5:02
false state normally closed contact
5:05
allows signal to pass through it. As a
5:08
result this output one will be true. So
5:11
this in this way we have implemented nor
5:14
logic gate.
5:17
Similarly we can also implement n logic
5:20
gate here. So I will right click and I
5:23
will insert one more network below it.
5:26
And then we will here implement nan
5:30
logic gate. So we will uh draw a ladder
5:33
diagram to implement nan logic gate. So
5:36
for nan logic gate
5:39
either of the input should be false.
5:44
So for that we will use normally closed
5:47
contacts but in this case we will
5:51
connect them in parallel.
6:12
[Music]
6:13
So here I will insert an or very close
6:15
contact and then I will click here and
6:18
here you can see insert the gate and
6:21
contact parallel.
6:23
So in this way
6:26
so in this way we have connected these
6:28
two normally closed contacts in parallel
6:31
with each other. So this will be input
6:35
three. Okay. And this will be
6:43
input four.
6:46
And then we need to connect a coil here.
6:48
So I will click here and then insert
6:51
coil.
6:53
And this coil will be output
6:57
two.
6:59
Okay.
7:01
So for output two to be on either of the
7:04
inputs should be false.
7:07
So if a if input three is true then the
7:12
signal will not flow through this this
7:15
input three will not allow signal to
7:17
pass through this. As a result this
7:20
output two will not be true. But if
7:23
input four is false if input three is
7:26
true but input four is false. So this
7:29
input four is a normally closed contact.
7:32
So in false state, it will allow signal
7:34
to pass through it. As a result, this
7:37
output two will be true. Similarly, if
7:40
input four is true, the signal will not
7:43
pass through this. But if input three is
7:46
true or false, the signal will pass
7:48
through this. As a result, this output
7:50
two will be true.
7:53
And in case if both the inputs are true
7:56
then also the signal will pass through
7:59
this and output two will become true.
8:02
And if both the inputs are true so these
8:05
two inputs these two contacts are
8:07
negated contacts normally closed
8:09
contacts in true state it will not allow
8:12
signal to pass through it. As a result
8:15
the output two will not become true. It
8:17
will be false. It will be off. So at
8:21
least one input should be false then
8:24
only output two will be true.
8:27
So we will simulate this. We will
8:28
generate code
8:32
and then we'll log in.
8:40
Before login,
8:44
we need to go to the uh
8:53
before going uh before login we need to
8:56
go to online and start simulation here
8:59
and then we'll go online. Yes.
9:17
after that we will start here.
9:21
As you can see here for
9:25
for this uh nor logic gate both the
9:28
inputs are false. Input one input one is
9:31
false. Input two is also false. And you
9:35
can see output one is true. So for
9:38
output one to be true, these both inputs
9:41
should be false. So if I turn input one
9:45
on, we will uh keep it true and then go
9:48
to debug and write values. You can see
9:51
here input one gets true. It will not
9:54
allow signal to pass through this. As a
9:57
result, this output one becomes false.
10:00
Similarly, we will turn it off and turn
10:03
on input two. We'll go to debug and
10:05
write values. So, as you can see here,
10:08
input one is false, but input two is
10:10
true. So, this is also normally close
10:13
contact. It will not allow signal to
10:15
pass through this. As a result, the
10:17
output one gets off. And similarly, if
10:21
we turn on both these inputs,
10:24
you can see output one does not get on.
10:26
It remains off. Why? Because for output
10:29
one to be on both the inputs should be
10:31
off. Okay. So for nor logic gate the
10:34
output will be on when both the inputs
10:37
are false. So when I turn off input one
10:39
and input two
10:41
you can see here output one becomes
10:44
true. Similarly
10:46
for n logic gate this output two will be
10:49
true if any one of the input is true.
10:53
Sorry if anyone at least one input
10:56
should be false. You can see here input
10:58
three is false and input four is also
11:01
false. You can see output two is true.
11:03
So if I turn on input three,
11:08
output two remains true. And if I turn
11:12
on
11:14
input four and turn off input three,
11:18
the output remains true because at least
11:21
one input is false. At least one input
11:25
is false.
11:27
So when I turn on both the inputs,
11:30
when I turn on both the inputs here,
11:34
the output two becomes false. So for
11:37
output two to be true, at least one
11:40
input should be false. Then only the
11:42
output two will be true. It was all
11:45
about this example. Thank you for
11:47
watching.
11:50
[Music]