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CODESYS Tutorials: Basic Logic Gates for Students
Oct 17, 2025
Learn basic logic gates in CODESYS with this tutorial for students learning PLC programming and automation fundamentals.
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0:00
[Music]
0:06
Hello everyone, welcome to automation
0:08
community. Today in this video we are
0:12
going to discuss about logic gates that
0:14
is and or and not. We will not
0:17
understand their logic only but also see
0:21
how to implement and simulate them using
0:24
codesses. So let's start
0:27
and gate. The output of an AND gate will
0:30
be on when both inputs are on otherwise
0:34
the output is off. If we have two inputs
0:37
A and B then both the inputs should be
0:41
on then only the output Y will be on. As
0:44
you can see in the table when the state
0:46
of A and B is zero that is both the
0:50
inputs are false then the output is
0:53
false. And then you can see when a is
0:56
false and b is true then the output is
1:00
false. And then you can see a is true b
1:03
is false then also the output is false.
1:06
So for output y to be on both the inputs
1:10
should be on then only the output y will
1:13
be on. If one of the input is false then
1:16
the output will not be true. So for the
1:20
output Y to be true both the inputs or I
1:24
can uh say like that all the inputs
1:27
should be on then only the output Y will
1:30
be on. Similarly for the or logic gate
1:34
the output of an or logic gate will be
1:37
on when any one of the input is on. That
1:40
means if we have two inputs A and B then
1:46
then if any one of the input is true the
1:49
output Y will be true. If A is true B is
1:52
off A is on and B is off then output Y
1:55
will be on. If A is off B is on then
2:00
also the output Y will be on.
2:03
As you can see in the table when both
2:05
the inputs are false the output Y will
2:08
be false. And you can see if B is true
2:12
and A is false then the output Y is
2:16
true. And when A is true and B is false
2:20
then also the output Y is true. And if
2:24
both the inputs are true then also the
2:26
output Y is true. So at least one input
2:30
should be true. Then only the output Y
2:32
will be true. And then we have node
2:35
logic gate that is similar to the
2:37
normally closed contact that we have
2:39
discussed in the uh previous video. The
2:42
output of node gate will be on when
2:45
input is off and vice versa. That means
2:49
when the state of input is true then the
2:52
state of output will be false and when
2:56
the state of uh input will be false then
2:59
the state of output will be true. That
3:02
means when input is true, output will be
3:05
false and when input is false, the
3:06
output will be true. So let's move to
3:09
codices where we will draw ladder
3:12
diagrams implement these logic gates one
3:14
by one. So firstly we will start with
3:17
and gate then or gate and then not gate.
3:21
I will open cortices here.
3:33
Let's create create a new project here.
3:38
I will change the name to logic gates
3:43
and choose the template as standard
3:45
project and click on okay.
3:50
You need to uh set the programming
3:52
language here as ladder logic diagram.
3:55
Click on okay.
4:01
Firstly we need to go to the PLCRG
4:04
double click on it and you can see here
4:06
we can uh uh here we will draw the
4:09
ladder diagram. So firstly
4:19
so firstly we will insert a normally
4:21
open contact and let's say it's
4:26
input
4:29
one.
4:32
Okay.
4:34
And then we are implementing and logic
4:38
gate. So when we are implementing and
4:40
logic gate, we will connect two inputs,
4:44
two contact, two normally open contacts
4:46
in series, one after the other. So I
4:50
will insert one more
4:52
normally open contact here.
4:55
and change its name to input two.
5:00
Click on okay. And then I will click
5:03
here
5:05
and then only I can insert a coil. And
5:07
this coil will be output
5:13
one.
5:15
Okay.
5:17
So this is a ladder diagram for add
5:19
logic gate. In this way you can you can
5:21
you know uh implement add logic gate. So
5:24
for this output one to be true both the
5:27
inputs should be true. If input one is
5:29
true, input two is false then the output
5:32
will not be true. And if input one is
5:36
false and input two is true the signal
5:39
will not flow through this as a result
5:41
this output one will be false. So for
5:44
output one to be true both these inputs
5:47
when input one is true the signal will
5:50
flow through this. When input two is
5:52
also true the signal will flow through
5:54
this as a result this output one will
5:56
get true.
5:58
After that
6:01
I will insert uh network below and here
6:05
we will implement or logic get. So here
6:09
I will insert a contact here
6:13
and this will be input
6:18
three.
6:20
So in this network we will be
6:22
implementing
6:24
this is input
6:28
three. Okay. So in this network we are
6:32
going to implement or logic gate or
6:35
logic gate. Okay. So to implement our
6:38
logic gate we have to you know connect
6:41
the normally open contacts in parallel.
6:44
So if this is uh a so b should be here
6:49
here should be b. So we need to you know
6:52
open the contact open the this uh branch
6:56
insert branch and then
6:59
and then click here and then add a
7:02
normally open contact like this.
7:06
We can also and then we need to insert a
7:09
coil. So we have inserted a coil but
7:12
this normally open contact will be as
7:16
input
7:18
four. Input four. Okay. So we need to
7:23
connect this input four like this. So in
7:26
order to connect this we have here that
7:29
is
7:33
or we can simply insert this like this.
7:35
I will delete this
7:42
and then I will click here.
7:56
like this and then I will insert a coil
7:59
here.
8:01
I can uh you know use this
8:05
uh
8:21
okay so this is input three and we need
8:24
to connect one more normally open
8:26
contact in parallel. So here we can use
8:29
this insert contact in parallel
8:33
and this normally open contact will be
8:38
input
8:40
four.
8:42
Okay.
8:44
And then we will insert a coil and this
8:47
coil will be output
8:51
two.
8:52
Okay.
8:55
So for output two to be on one of the
8:58
inputs at least one input should be on.
9:01
If input three is on the signal will
9:04
pass through this and output two gets
9:06
on. If input three is off then the input
9:10
four should be on. Then the signal will
9:13
pass through this. As a result this
9:16
output two gets on.
9:18
So if the both inputs are true then the
9:21
signal will pass through these uh
9:23
contacts. As a result, the output two
9:25
gets on. So if none of the input is
9:28
true, then the output two does not get
9:31
on. So at least one input should be on
9:34
so that output two gets on. After that I
9:38
will right click and insert network
9:40
below. And here we need to you know
9:43
implement not logic get. So we will
9:46
insert a normally negated contact,
9:48
normally close contact and a coil. So I
9:51
will click here and add a coil. So this
9:55
will be
9:57
input
9:59
five. Okay. And then this coil will be
10:05
output
10:06
three. So for output three to be on,
10:09
input five should be off. And when input
10:13
five is off, the output 3 is on. And
10:16
when input five is on the output three
10:20
will be off.
10:23
This is output three. Okay.
10:28
So let's start the superition here. I
10:30
will generate the code here
10:34
and then log in.
10:53
Before that I need to go to you know uh
10:56
online and start simulation and after
10:58
that I will log in. Yes.
11:05
And then start.
11:16
As you can see here input one and input
11:19
two both are off and output one is also
11:24
false. So when I turn on input one go to
11:27
debug and write values the output one
11:31
does not get on. So if input one is on
11:35
if input one is true and output two
11:38
input two is false then output one is
11:41
also false. So we need to turn on this
11:44
input two as well.
11:46
So I will click here it gets true and
11:49
then go to debug and write values and
11:51
after that you can see output one gets
11:54
true.
11:56
So for output one to be on both the
11:59
inputs should be false. So if I turn off
12:01
the input one debug and write values you
12:06
can see
12:09
you can see output one gets false. So
12:12
this is and logic gate and means input
12:14
one and input two both should be on then
12:18
only the output will be on. So moving
12:21
forward to the all logic gate here. So
12:23
input three and input four. So as you
12:25
can see here input three and input four
12:29
both are false
12:32
and this output two is also false. So
12:35
when I turn on this input three when I
12:38
turn uh click here it gets true and then
12:41
go to debug and write values. So as you
12:44
can see here where input three is true
12:46
output two gets true and when I turn on
12:48
input four as well
12:54
output two remains true.
12:58
So and after that
13:14
output two remains true. So when I turn
13:16
on of this input P input three when I
13:20
turn off this input P
13:23
the output two remains true. So at least
13:26
one of the two inputs should be true.
13:28
Then only output two remains true. So
13:31
when I turn off input four as well when
13:34
I turn off it,
13:36
output two gets off. So output two gets
13:40
on when one of the input gets true. And
13:42
moving towards the uh not logic gate,
13:46
you can see this input five. This input
13:48
five is false but output three is true.
13:53
So
13:55
when I input five is true,
14:04
input five is false but the output 3 is
14:07
true. And when I turn on this output
14:09
five, I will debug at write values. You
14:12
can see output three gets off. And when
14:15
I uh turn off this input five,
14:19
the output three gets true. It was all
14:23
about this example. Thank you for
14:25
watching.
14:27
[Music]