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Master the design of XOR and XNOR logic circuits in PLCs using CODESYS! This tutorial guides you through step-by-step ladder logic implementation, with real automation examples and simulations. Perfect for beginners and engineers looking to advance PLC programming skills.
Topics covered:
What are XOR & XNOR Gates?
CODESYS ladder logic setup
Real-time PLC simulation
Applications in industrial automation
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0:00
[Music]
0:06
Hello everyone, welcome to automation
0:08
community. Today in this video we are
0:12
going to discuss about derived logic
0:14
gates that is exor and xn not. So let's
0:18
start
0:20
exor gate. The output of a two input
0:23
exor gate will be on when one input is
0:26
on and other input is off. As you can
0:30
see in the table, the output Y is on
0:34
when only one input is true. Then only
0:38
output Y will be on. So when both the
0:41
inputs are off, the output Y will be
0:44
off. And when only one input is on, that
0:47
means A is off, B is on or one is on, B
0:50
is off, then the output Y will be on.
0:54
And if both the inputs are true, if both
0:56
the inputs are on, then the output Y
0:59
will be off.
1:01
Similarly, X or X ex X nor the output is
1:06
on when both inputs are the same that is
1:09
both zero or both one. As you can see in
1:13
the table, when both the inputs are
1:15
false, the output Y is true. And when
1:18
the states of the two inputs is
1:21
different that means one is off and
1:23
another is on or one is on and another
1:27
is off then the output Y will be off and
1:30
when both the inputs are true when both
1:33
the inputs are on then the output Y will
1:36
be on. So now let's move to cordises
1:39
where we will draw a ladder diagram for
1:41
these two gates and also simulate them.
1:46
So I will open cortices.
1:58
I will create a new project.
2:01
Standard project. Okay.
2:18
So we'll go to PLCPRG.
2:21
So here we will draw the ladder diagram.
2:23
Firstly for exor gate
2:27
as you know for exor logic gate the
2:31
output Y will be on if the states of the
2:35
inputs are different.
2:38
When the states of the two inputs are
2:41
same the output Y will not be on. So
2:44
either one input should be on and
2:46
another input should be off or first
2:48
input should be off and another input
2:50
should be on then only the output Y will
2:53
be on. If the if both the inputs are
2:56
true the output will not be true and if
3:00
both the inputs are false the output uh
3:02
will not be on. So firstly we will be
3:07
using both normally open contacts as
3:10
well as normally closed contacts
3:13
for the output. So firstly we will
3:16
insert a normally open contact and then
3:20
we will insert a negated contact here
3:23
but in parallel
3:26
and then we will insert here a normally
3:28
closed contact and here we will be
3:31
inserting a normally open contact. and
3:34
then we will insert a Y. So we'll
3:37
understand what we have done here. So
3:40
this normally open contact will be input
3:43
one. Okay.
3:47
And then this will be input two.
3:58
And we have used a normally open contact
4:01
for input one and a normally closed
4:04
contact for input two. And this coil
4:06
will be output one.
4:11
So output one will be on when input one
4:14
is on and input two is off. So when
4:17
input one is on it will allow signal to
4:21
pass through this and when input two is
4:23
false this is a normally closed contact.
4:26
So in false state the signal will pass
4:28
through this as a result this output one
4:30
will be true. Similarly
4:33
when input two is true and input one is
4:36
false then also output one will be true.
4:39
So we'll use this normally close contact
4:42
for input
4:44
two and this normally closed contact for
4:49
input one. Input one.
4:54
So here when input one is false and
4:57
input two is true the output one will be
5:00
true. If both the inputs are true input
5:02
one is true input two is true the signal
5:04
will not pass through this input one is
5:06
true input two is true the signal will
5:08
not pass through this input two as a
5:10
result the output one will not be true.
5:14
So for input one to be true the states
5:17
of both the inputs should be different.
5:20
One should be true, first one should be
5:21
true, second one should be false or
5:24
first one should be false and second one
5:26
should be true. So the states of these
5:28
two inputs should be different and then
5:31
only the output one will be on. So for
5:34
exor gate for exor gate only one input
5:39
should be true and another should be
5:41
false. Either input one should be true
5:43
or input two should be true. Similarly,
5:46
we will now draw a ladder diagram and
5:49
implement XNOR gate. So, I will right
5:52
click here and insert network below. So,
5:55
here we will draw the ladder diagram for
5:57
XNOR gate. For XNORT
6:02
for XNORET,
6:04
the output will be true if the states of
6:08
both the inputs are same. either all the
6:11
inputs are true or both the inputs are
6:14
false.
6:16
So here we will insert a normally open
6:19
contact
6:20
and then I will insert a nated contact
6:25
in parallel and then we will add a
6:27
normally open contact here and here we
6:30
will add a normally closed contact and
6:32
then we will insert a coil.
6:35
So this normally open contact will be
6:39
input
6:41
three
6:46
and this normally open contact will be
6:49
input four.
6:53
And here if both the inputs are true the
6:56
signal will pass through this. As a
6:58
result this output two will be true.
7:03
And similarly if input three
7:09
is false and with that input
7:13
four is also false. These both inputs
7:17
are normally closed contacts. In false
7:20
state the current will pass through
7:21
this. The signal will pass through this.
7:23
As a result this output two will become
7:25
true.
7:27
So if the states are different for
7:30
example input three is on input four is
7:32
off the the signal will not not pass to
7:35
this. Similarly here input three is true
7:39
the signal will not not pass to this the
7:42
output two will not be true.
7:45
So for XNOR logic gate for output to be
7:49
all the states of the two inputs should
7:52
be same either both the inputs are true
7:56
the signal will pass through this or
7:58
both the inputs are false the signal
8:00
will pass through this. So now let's
8:03
generate code here
8:06
go to online and click on simulation.
8:09
After that we will go login by clicking
8:12
here.
8:13
Okay.
8:19
After that I will start.
8:21
So as you can see here for output one
8:24
this is ex logic. Both the inputs are
8:27
false. Input one is false. Input two is
8:30
false and output one is also false.
8:35
So for output one to be on the states of
8:38
the two inputs should be different. It
8:40
should be different. One should be on,
8:42
another should be off. If input one is
8:44
true, the input two should be false. So
8:47
let's see, go debug and write values. So
8:50
as you can see here, input one is true,
8:53
out input uh two is false and the output
8:57
one becomes true. And similarly, when
8:59
input one will be false and input two
9:02
will be false, then also output one will
9:05
be true. So as you can see if both the
9:08
inputs are true, if both the inputs are
9:11
true, input one is true, input two is
9:13
true, then the output one will not be
9:16
true. This is the exor logic gate. Only
9:20
one input should be true. Only one input
9:23
should be true and another should be
9:25
false. Only one input should be true.
9:28
Only one input should be true. This is
9:31
false. Input one is false. Input two is
9:34
true. Let's debug it.
9:36
And you can see output becomes true. And
9:39
for XNOR logic gate both the inputs
9:43
should be either in true state or in
9:45
false state. And you can see here input
9:48
three is false. Input four is false. The
9:51
states of the two inputs are same. The
9:54
output is true. And when I turn on the
9:58
input three let's debug it. So as you
10:01
can see here the states of the two
10:03
inputs is different. output two becomes
10:06
false. And similarly, if I turn off
10:09
input three and turn off on input four
10:12
and let's debug it and you can see
10:14
output two is still false because the
10:17
inputs are different. The states of the
10:20
inputs are different. One is false and
10:22
another is true. Let's make both of them
10:25
true. I will debug it and you can see
10:28
both the inputs. Input three is true,
10:30
input four is true and the output
10:32
becomes true. And when I turn off one of
10:35
the input, output becomes false. And
10:38
when I turn off both the inputs, the
10:41
output becomes true again. So for XNOR
10:45
logic gate, the output becomes true only
10:48
when the states of the both the inputs
10:51
are same. Then only the output becomes
10:53
true. It was all about this example.
10:56
Thank you for watching.
11:00
[Music]
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